Products
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Part number
Power Bus Supply Voltage VM
Coil Current Spec
H-bridge Rds(on) (per phase HS+LS)
PWM Chopping Frequency
Microstep Capability
Current Decay Mode
Control Interface
Current Regulation
Dead Time
Quiescent/Sleep Current (Iq/Isleep)
Protection Features
Fault Feedback
Logic Interface Level
Special Features
Package
ST6610Operating 4.2~36V; Abs. Max 45V
Per-phase RMS continuous 2.5A, peak 5A
HS+LS each 0.2Ω (combined ~0.4Ω) @VBB=24V, Iout=0.5A, 25℃
Chopping PWM kHz not published (driven by 12MHz CLK base)
Up to 256 microstep (MS1/MS2 pins: 00=1/8, 01=1/2, 10=1/4, 11=1/16)
Decay mode not published (built-in constant-current chopping)
STEP/DIR interface, UART one-wire interface (readback/disable power-down), MS1/MS2, ENABLE, HOLDEN
REF analog voltage sets current (0.5~2.5V, Irms=0.092×VREF/RSENSE); auto power-save to 50% on hold
Dead time 100ns (fixed)
Operating IVBB typ 8.0mA/max 11mA (VBB=24V, CLK=12MHz); IO 300µA; auto power-save to 50% on hold
OTP(156℃,26℃ hyst), UVLO(VBB 4.2V/VREG 3.5V/VIO 2.5V), output short-circuit, OCP
FLAG1 diagnostic output, FLAG2 configurable position pulse output
VIO logic 3.0~5.5V (3.3V/5V); built-in 5V VREG LDO
AGC auto-gain torque compensation, silent low vibration, UART one-wire interface, hold auto-power-save, charge pump, 5V LDO
eTSSOP28
ST6609Operating 4.7~36V; Abs. Max 40V
Per-phase RMS continuous 2A, peak 4A
HS+LS each 0.2Ω (combined ~0.4Ω) @VBB=24V, Iout=0.5A, 25℃
Chopping PWM kHz not published (driven by 12MHz CLK base)
Up to 256 microstep (MS1/MS2 pins: 00=1/8, 01=1/2, 10=1/4, 11=1/16)
Decay mode not published (built-in constant-current chopping)
STEP/DIR interface, MS1/MS2 resolution, CLK (4~18MHz), ENABLE, HOLDEN
REF analog voltage sets current (0.5~2.5V, Irms=0.092×VREF/RSENSE); auto power-save to 50% on hold
Dead time 100ns (fixed)
Operating IVBB typ 7.8mA/max 11mA (VBB=24V, CLK=12MHz); IO 300µA; auto power-save to 50% on hold
OTP(156℃,26℃ hyst), UVLO(VBB 4.2V/VREG 3.5V/VIO 2.5V), output short-circuit (VM/GND), OCP
FLAG1 error flag output, FLAG2 position output (pulse per 4 step angles)
VIO logic 3.0~5.5V (VIL<0.3×VIO, VIH>0.7×VIO); built-in 5V VREG LDO
AGC auto-gain torque compensation, silent low vibration, hold auto-power-save, charge pump, 5V LDO
QFN28(5×5), e=0.50mm
ST62093.3V logic / 5V motor (VDD5 3.0~5.5V, AVDD3/DVDD 2.7~3.6V); Abs. Max 4.0V/6.0V
Per-channel continuous 0.8A (Absolute Maximum Istm=1.0A)
HS+LS combined 1.2~1.8Ω @Io=100mA, 25℃
- (micro-step output PWM freq/resolution set via SPI register; chopping kHz not published)
Up to 256 micro-step/channel (SPI registers MICROAB/MICROCD configure sine-wave division)
- (PWMMODE register via SPI sets micro-step PWM; decay mode not specified)
SPI serial interface (CS/SCK/SIN/SOUT), driver params configurable
SPI digital registers configure coil current/microstep (no REF pot pin)
- (dead time not published)
DVDD/AVDD standby <10µA (RSTB=1); VDD5 standby <10µA (RSTB=1); DVDD/AVDD operating 7~20mA (RSTB=0, no-load); VDD5 operating 0.1~1mA (RSTB=0, no-load)
OTP TSD(155~180℃,26℃ hyst), UVLO1(DVDD/AVDD 2.27V,0.2V hyst)/UVLO2(MVCCA/MVCCB/VDD5 2.20V,0.2V hyst)
SOUT (SPI readback), PLS1/PLS2 position pulse outputs
DVDD/AVDD 3.3V logic (0.54×DVDD~1.36×DVDD); VDD5 5V
256-microstep ultra-silent, 2 open-drain LED drivers, α/β motor phase correction, position pulse output (camera zoom/focus)
QFN44L(5×5), e=0.35mm