Products
Product image
Part number
Max Sample Rate
Protocols (S/PDIF+AES3)
Input Channels
Recovered Clock Jitter
5V Support (VL)
Control Interface
Output Format
Package
Temp. Range
ST841632 kHz ~ 192 kHz (192 kHz max)
Compatible with IEC60958, S/PDIF, EIAJ CP1201, AES3 (full S/PDIF + AES3 support)
8:2 S/PDIF input mux (8 inputs RXP[7:0] select 2); hardware mode can select AES/SPDIF input; differential input supported
RMCK output clock jitter typ 200 ps RMS
Yes: VL logic interface supply +3.3V or +5.0V
Software mode: SPI™ and I²C; hardware mode (pure pin configuration)
Serial digital audio output; general output format supports left-justified / right-justified / I²S etc. (multi-bit, programmable bit clock & left/right clock polarity); supports AES3 direct output format (V/U/C bits readable)
TSSOP28
-40°C ~ +85°C